Non-volatile memory has divided for applied reasons into four fairly distinct product segments. These include mask read only memory, electrically erasable programmable read only memory (EEPROM), erasable programmable read only memory (EPROM) and the, EEPROM-EAROMs. Different types of devices have been developed for specific applications requirements in each of these segments. The EEPROM basic technologies used to manufacture electrically reprogrammable ROMs all utilized to some extent Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-silicon dioxide interface and into the oxide conduction band. EEPROMs using field effect transistors with floating-gate structures are programmed and erased by electrically storing and removing charges from the dielectric-insulated floating gates. The digital information stored in EEPROMs is read by differentiating between the source-drain impedance presented by a charged (high voltage threshold Vt) floating gate and an uncharged (low floating gate) floating gate.
In EEPROMs, electrons are transferred to a floating gate electrode through a dielectric layer overlying the channel region of a transistor. The EEPROMs is programmed by applying a high positive voltage to the control gate electrode and a lower positive voltage the drain region. Electrons are transferred from the tunneling window region to the floating gate electrode. The EEPROMs is erased by grounding the control gate, and applying a high positive voltage to either the source or drain regions of an enhancement transistor. Under the conditions, electrons are removed from the floating gate and into either the source or drain regions.
A conventional methods of forming EEPROM is described herein. As shown in FIG. 1, a semiconductor substrate 1 is p type single crystal with &lt;100&gt; crystallographic orientation. First, a thick field oxide region (FOX) 3 is formed for the purposes of isolation. The FOX 3 region is created via photolithography and dry etching steps to etch a silicon nitride-silicon dioxide composite layer. After the photoresist is removed and wet cleaned, a thermal oxidation in an oxygen steam ambient is used to form the FOX 3 region, at a thickness about 7000-9000 angstroms.
Then a first photoresist is patterned on the substrate 1. Subsequently, an ion implantation is used to form a buried N.sup.+ (BN.sup.+) source and drain region of a stack transistor. The dosage of the implantation is 2-4E15 atom/cm.sup.2, the energy of the implantation is about 50-80 KeV. Then the first photoresist is stripped after the source and drain regions are formed.
As shown in FIG. 12, a mask 31 is patterned on the substrate to define an active region. Then a mask 29 is formed to cover a portion of the active region and define a buried N.sup.+ (BN.sup.+) source and drain region.
Turning to FIG. 2, a silicon dioxide layer 5 is formed on the substrate 1 to act as a gate oxide 5. The silicon dioxide layer 5 is formed by using an oxygen-steam ambient, at a temperature between about 800 to 900.degree. C., to a thickness about 200-400 angstroms. A second photoresist 7 is then patterned on the field oxide 3 and on the silicon dioxide layer 5. An opening is generated in the silicon dioxide layer 5 by using a wet etching to etch the silicon dioxide layer 5. The photoresist 7 is then removed.
As shown in FIG. 13, a mask 33 is patterned on the substrate to expose a portion of the N.sup.+ (BN.sup.+) source and drain region and to define a tunnel region. A mask 34 is used to define a first polysilicon layer.
Turning to FIG. 3, a thermal treatment is performed to the substrate 1. This step of the process is used to create a tunnel oxide 9. Similarly, the tunnel dioxide 9 is formed by using an oxygen-steam ambient, at a temperature between about 800.degree. to 900.degree. C., to a thickness about 90-110 angstroms. The silicon dioxide layer 5 became thicker due to the thermal treatment. A first polysilicon layer 11 is then formed over the silicon dioxide layer 5, tunnel oxide layer 9 and the field oxide regions 3. The first polysilicon layer 11 is formed using conventional chemical vapor deposition (CVD), which is served as a floating gate. Then an etching step is used to etching the first polysilicon layer 11 to define the floating gate of the EEPROM.
Referring next to FIG. 4, a dielectric layer 13 is formed on the first polysilicon layer 11 for the purpose of isolation. The dielectric layer 13 is formed of oxide. Next, an etching step is used to etch the dielectric layer 13 to serve as an isolating layer. Subsequently, a second polysilicon layer 15 is formed on the dielectric layer 13. After the polysilicon layer 15 is formed, photolithography and etching are performed to etch the polysilcon layer 15 to define a control gate 15 and a pass gate 19.
Turning to FIG. 5, a second dielectric layer 21 is subsequently deposited on the substrate 1, control gate 17 and on the pass gate 19 to a thickness about 4000-7000 angstroms. A contact window 23 is then created by using photolithography and etching process. The second dielectric layer 21 is composed of BPSG. Finally, a metal layer 25 is formed on the second dielectric layer 21 and the contact window 23 is filled with the metal layer 25 to serve as a bit line contact.
FIG. 14 shows a mask 35 is patterned to define a second polysilicon region and a mask 36 to define a contact hole in the active region. A mask 37 is used to define a metal bit line region.
However, to increase the density of semiconductor devices has been the trend in integrated circuit technology. In order to increase the packaging density, it trends to shrink the scale of a device. It follows then that the semiconductor devices, such as transistors and capacitors, must be made smaller and smaller. Unfortunately, one area which poses as a significant barrier to the miniaturization of semiconductor devices is photolithography. The photolithography has a limitation because of the resolution of the photolithography.